Test Engineering Manager (Teradyne UltraFlex) for Core Switching Group (CSG)

This position is working from the San Jose office and managing a 10+ member team…

Responsibilities:

· Manage high talented test engineering team (10 TDE) to support switches and router product line

· Strong technical background to look ahead of new test methodologies to meet new challenges.

· Ability to evaluate ideas and concepts for high-speed and high-power new products. Work with various functional teams (product engineering, design, marketing, etc…)

· Need to work with design centers and CMs in multiple time zones.

· Communicate with overseas (Asia) Product and Test Development engineers to resolve manufacturing issues.

· Strong collaborative and communication skills are must.

· Able to lead the team with engineering perspective and solid management skills.

· Will need to look ahead for new technology/new requirements and collaborate with the design team.

· Will be a combination of management and hands-on. Hands-on testing will be minimal but candidates will need an understanding of engineering language when difficulties arise with the tester and will need to know how to assist engineer

· 5% of Test work and 50% of Engineering component, the rest will consist of a management portion.

· Department candidate will work in: Core Switching Group (CSG).

· The Test Manager will manage 10 engineers in Irvine, CA, and San Jose, CA. Will grow the team in 2023.

Required Experience

· 10+ years of direct experience on a production semiconductor manufacturing test floor.

· At least five years’ experience in management or lead role.

· A strong business sense to guide the team in delivering the most cost-effective test solutions.

· Must have strong engineering background and management skills.

· Must have with ATE (Teradyne UltraFlex PA); knowledge of Advantest 93k would be a benefit.

· Good understanding of ATE test hardware. Need to review the design with team members to develop robust and production-worthy hardware.

· Have in-depth understanding of ATE to guide ATE team in developing test methods with both quality and cost under consideration.

· Good understanding of programming and able to prepare spec for the script for team members to implement.

· Detailed knowledge on signal integrity concerning PCB layout and other hardware designs; able to evaluate simulation results.

· Thorough background on Mix-signal device test; experience on SerDes (>100G) Test is a plus.

· Hands-on experience on wafer sort probing both on hardware and software.

· For layers 2&3 –need to focus more on physical layer. For the hardware side, needs to have strong knowledge on high speed. They will be dealing with over 100g and they will need to have a strong understanding of sequence integrity.

· Needs to have strong background in high-speed knowledge overall.

· Focus on high speed and single integrity. Needs to understand the theory and technology around single integrity (Teradyne UltraFlex, Interface protocol, Jtag)

· Bachelor’s degree in Electrical/Electronic engineering. Master’s degree is preferable.

Location: San Jose, CA (relocation assistance is available)

Type: Direct-hire Fulltime (work on-site)

Submit resume to jobs@OSIengineering.com

Abel Lara | 408.550.2800 x119

Abel@OSIengineering.com